Cost/performance evaluation for a 3D symmetric NoC router

In this paper, we propose a wormhole router architecture for symmetric 3D-mesh Networks-on-Chip (NoCs) with virtual channels. It uses the credit-based flow control mechanism and dimension-order routing XYZ algorithm. With priority-based scheduling, our 3D on-chip communication model can support the management of different levels of quality-of-service. The router is implemented on FPGA device using the Xilinx ISE software. Various designs were synthesized to verify the capability of our router. From the implementation results, the proposed router architecture enables a higher data rate and low latency at a reasonable power and area overheads. Furthermore, we demonstrate an analysis and comparison of the cost and performance results between the 2D and 3D designs.