Characterization of an Associative Memory Chip in 28 nm CMOS Technology

This paper presents the characterization of the new Associative Memory chip (version 7) designed and fabricated in 28 nm CMOS. The design aims at: enhancing links from/to FPGAs; increasing bandwidth thanks to full custom LVDS transceivers; and reducing power consumption and silicon area by means of new memory cells designed with full-custom approach. The design was submitted in December 2016; the prototypes were fabricated and packaged in a 17 × 17 Ball Grid Array (BGA) standalone package. Prototype characterization confirms the chip functionality. The final chip will be assembled in a System In Package (SiP) together with a bare FPGA die.