A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnectsat three local interconnectlayers is described. For high density, a novel self-aligned contact over active gate processand eliminationof the dummy gate at cell boundaries are introduced. The transistors feature rectangular finswith 7nm finwidth and 46nm finheight, 5 th generation high-k metal gate, and 7 th -generation strained silicon. Four or six workfunction metal stacks are used to enable undoped finsfor low Vt, standard Vt and optional high Vt devices. Interconnectsfeature 12 metal layers with ultra- low-k dielectricsthroughout the interconnectstack. The highest drive currents with the highest cell densities are reported for a 10nm technology.