Temperature assessment of Si1-xGex source/drain heterojunction NT-JLFET for gate induced drain leakage ‒ A compact model

Abstract In this paper, we have investigated the impact of temperature (T) and drain bias voltage (Vds) on gate induced drain leakage (GIDL) in SiGe Source/Drain heterojunction silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET). We developed a temperature dependent model for surface potential, electric field EZ, L-BTBT induced IGIDL and full drain current Ids using 2-D Poison equation with suitable boundary conditions. We have also examined impact of temperature (activation energy) and drain bias voltage (electric field) on L-BTBT induced IGIDL. It is found that the increase in drain bias voltage causes 31.1% rise in IGIDL and elevation in temperature has 29.4% increase in IGIDL. Furthermore, we have examined impact of temperature on transconductance (gm) and output conductance (gd). The results demonstrated that temperature and drain bias voltage has significant impact on SiGe S/D NTJLFET, however, it is considerably less than the NTJLFET.