Charge Buildup and Spatial Distribution of Interface Traps in 65 nm pMOSFETs Irradiated to Ultra-high Doses

In this work, a commercial 65 nm CMOS technology is irradiated at ultra-high ionizing doses and then annealed at high temperature under different bias conditions. Experimental results demonstrate the high sensitivity of pMOSFETs to radiation-induced short-channel effects, related to the buildup of defects in spacer dielectrics. We find that the charge buildup in the spacers is insensitive to applied source-to-drain electric field, but the generation and/or annealing of interface traps strongly depends on applied drain bias and channel length. Static DC and charge pumpingmeasurements indicate a high density of interface traps in the lateral source/drain extension regions. The worst-case bias condition corresponds to the application of a large drain-source voltage, due to the lateral electric field driving hydrogen from the spacers towards the source extension and the channel. The consequent differences in growth and annealing rates of interface traps leads to a large asymmetric degradation of the short-channel transistors. Technology computer-aided design simulations are used to qualitatively confirm the proposed degradation model.