Testing ADC's at sample rates from 20 to 120 MSPS

Results are presented from an ongoing program to test the performance of high-speed analog-to- digital converterssuitable for use at the Superconducting Super Collider(SSC) and Large Hadron Collider(LHC). For each device a large number of parameters is measured, such as number of effective bits, noise level, aperture jitter, nonlinearity, analog bandwidth, and total harmonic distortion. Results from a variety of 8-b and 10-b devices are presented. >