Active Memory Cube: A processing-in-memory architecture for exascale systems
2015
A processing-in-
memory architecturefor exascale systems R. Nair S. F. Antao C. Bertolli P. Bose J. R. Brunheroto T. Chen C.-Y. Cher C. H. A. Costa J. Doi C. Evangelinos B. M.
FleischerT. W. Fox D. S. Gallo L. Grinberg J. A. Gunnels A. C. Jacob P. Jacob H. M. Jacobson T. Karkhanis C. Kim J. H. Moreno J. K. O’Brien M. Ohmacht Y. Park D. A. Prener B. S. Rosenburg K. D. Ryu O. Sallenave M. J. Serrano P. D. M. Siegl K. Sugavanam Z. Sura Many studies point to the difficulty of scaling existing computer architectures to meet the needs of an exascale system (i.e., capable of executing 10
floating-pointoperations per second), consuming no more than 20 MW in power, by around the year 2020. This paper outlines a new architecture, the Active Memory Cube, which reduces the energy of computation significantly by performing computation in the
memory module, rather than moving data through large
memory hierarchiesto the processor core. The architecture leverages a commercially demonstrated 3D memory stack called the
Hybrid Memory Cube, placing sophisticated computational elements on the logic layer below its stack of
dynamic random-access memory(DRAM) dies. The paper also describes an Active Memory Cube tuned to the requirements of a scientific exascale system. The computational elements have a vector architecture and are capable of performing a comprehensive set of
floating-pointand integer instructions, predicated operations, and gather-scatter accesses across memory in the Cube. The paper outlines the software infrastructure used to develop applications and to evaluate the architecture, and describes results of experiments on application kernels, along with performance and power projections.
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