Optimization of high performance fully overlapped LDD (FOLD) MOSFET's

A computer aided model to optimize the performance of drain engineered MOS transistors is reported. Simple closed form expressions for the drain current, transconductance and transit time were derived. A comparative study of the device characteristics is made between the conventional, spacer LDD and Fully Overlapped LDD (FOLD) MOS transistors. Suitable fold finger designs were made to optimize the FOLD structures for lower transit time and better current driveability. The FOLD structure promises better performance and reliability in comparison with other structures.