A low-voltage low-power self biased bulk-driven PMOS cascade current mirror

A low-voltage low-power self-biased PMOS cascade current mirrorusing bulk driven technology is proposed in this paper. The proposed circuit is analyzed and simulated for various parameters including input/output characteristics, output resistance, current linearity, system dc transmission error(e), power consumption etc. The circuit is designed using GPDK 180nm CMOS process and the simulation is done using CadenceSpectre. The simulation results show that: the proposed circuit has very high current swing, high output impedance, enhanced current linearity and negligible e compared to its gate-driven and bulk-driven counterparts. Further, with the use of PMOS as an active resistance, the power consumption of the circuit is also reduced drastically. Thus the proposed design can be used widely in power efficient CMOS analog integrated circuits.