Characterization of SLVS Driver and Receiver in a 65 nm CMOS Technology for High Energy Physics Applications

This work is concerned with the design and characterization of an SLVS transmitter/receiver pair, to be used for I/O links in High Energy Physics applications. Core transistors with a power supply of 1.2 V have been considered in the design in order to mitigate the TID effects, due to the harsh radiation environment foreseen. The circuits have been implemented in a 65 nm CMOS technology. The prototype chip was designed and fabricated in the framework of the RD53 project and was completely characterized in the first quarter of 2016. The chip has been also irradiated with X-rays in order to evaluate the effect of the ionizing radiation on the signal integrity