Ultra-high-speed Interconnect Technology for Processor Communication

In order to improve the performance of storage systems and servers that make up the cloud, it is essential to have high-bandwidth interconnectsthat connect systems. Fujitsu has already marketed a CMOS high-speed interconnectproduct that works between CPUs for the UNIX server (SPARC M10). Its data transfer rate per signal line is 14.5 Gb/s. Further, Fujitsu is currently engaged in studies of a CMOS interconnectthat can operate at over 32 Gb/s per signal line to achieve a higher bandwidth interconnect. To realize higher speed, we developed a high-speed interconnectwith a loss-compensation performance higher than 30 dB at 32 Gb/s by integrating a series of features: a communication methodrequiring no high-frequency operation in a transmitter circuit, a wideband loss-compensation equalizer circuit in the receiver circuit, and a data-receiving method that does not require generation of a highly accurate sample clock. When these technologies are implemented in a CPU chip, it is possible to improve the entire performance of server systems to a level more than twice to a level more than twice as high as the current one. This paper introduces the features of these ultra-high-speed interconnecttechnologies for 32-Gb/s serial interconnectsimplemented by using 28-nm CMOS technology.