External I/O interfaces in sub-5nm GAA NS Technology and STCO Scaling Options

In this paper, the challenges of the I/O development roadmap are discussed. The impact of I/O application in FEOL scaling and 3D integration are evaluated. A cost-efficient circuit solution to the I/O implementation in a gate-all-around (GAA) nanosheet (NS) technology is proposed. The functionality verification and the relevant reliability concerns are assessed in a mature industrial CMOS process. Finally, to foresee the design strategies in future STCO scaling era, the impact of the fully back-side (BS) connections on I/O performance is investigated. Capacitance is doubled compared to front-side (FS) I/O due to the contributions from BS connection layers. The layout techniques can mitigate ~30% of the extra capacitance and the technology option of the deep trench isolation (DTI) is considered to reduce the extra capacitance to only ~8%.