A 1.75 mW 1.1 GHz Semi-Digital Fractional-N PLL With TDC-Less Hybrid Loop Control
2012
A 1.1 GHz semi-digital fractional-N PLL without the
time-to-
digital converter(TDC) whose resolution and linearity heavily depends on process and temperature variations is implemented in 65 nm CMOS. A hybrid loop control with a fully differential proportional-gain path and embedded
finite-impulse response(FIR) filtering achieves
linear phasetracking as well as good technology scalability, having a small analog loop filter area less than 0.01 ${\rm mm}^{2}$ . The use of the hybrid FIR filter not only suppresses out-of-band quantization noise of the $\
Delta\Sigma$
modulatorbut also improves the linearity of the proportional-gain path. The TDC-less semi-digital PLL consumes 1.75 mW from a 0.9 V supply voltage, achieving significant power reduction compared to conventional all-digital PLLs.
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