Clock Distribution and Readout Architecture for the ATLAS Tile Calorimeter at the HL-LHC
2018
The Tile
Calorimeter(TileCal) is one detector of the
ATLAS experimentat the
Large Hadron Collider(LHC). TileCal is a sampling
calorimetermade of steel plates and plastic scintillators which are readout using approximately 10,000 PhotoMultipliers Tubes (PMTs). In 2024, the LHC will undergo a series of
upgradestowards a High Luminosity LHC (HL-LHC) to deliver up to 7.5 times the current nominal instantaneous luminosity. The ATLAS Tile Phase II
Upgradewill accommodate detector and Data AcQuisition (DAQ) system to the HL-LHC requirements. The detector electronics will be redesigned using a new clock distribution and readout architecture with a fulldigital trigger system. After the Long Shutdown 3 (2024-2026), the on-detector electronics will transfer digitized hadron
calorimeterdata for every bunch crossing (~25 ns) to the Tile
PreProcessors(TilePPr) in the counting rooms with a total data bandwidth of 40 Tbps. The TilePPrs will store the detector data in pipeline memories to cope with the new ATLAS DAQ architecture requirements, and will interface with the Front End
LInk eXchange(FELIX) system and the first trigger level. The TilePPr boards will distribute the sampling clock to the ondetector electronics for synchronization with the LHC clock using
high-speed linksconfigured for fixed and deterministic latency. The
upgradedreadout and clock distribution strategy was fully validated in a Demonstrator system using prototypes of the
upgradedelectronics in several test beam campaigns between 2015 and 2018.
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