A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits
2017
Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive
design space exploration. Employing state-of-the-art reliability estimation methods makes this exploration un-scalable with the design complexity. In this paper we introduce a low-cost reliability analysis methodology that helps taking this key decision with less computational effort and orders of magnitude faster. Based on this methodology we also propose a selective hardening technique using a hybrid fault tolerant architecture that allows meeting the
soft-errorrate constraints within a given design cost-budget and vice versa. Our experimental validation shows that the methodology offers huge gain (1200 ×) in terms of computational effort in comparison with
fault injection-based reliability estimation method and produces results within acceptable error limits.
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