Architecture of the PSC-a programmable systolic chip
1983
In recent years, many
systolicalgorithms have been proposed as solutions to computationally demanding problems in signal and image processing and other areas. Such algorithms exploit the regularity and parallelism of problems to achieve high performance and low I/O requirements. Since
systolicalgorithms generally consist of a few types of simple processors, or
systoliccells, connected in a regular pattern, they are less expensive to design and implement than more general machines. This advantage is offset by the fact that a particular
systolicsystem can generally be used only on a narrow set of problems, and thus design cost cannot be
amortizedover a large number of units. One way to approach this problem is to provide a programmable
systolicchip (PSC), many copies of which can be connected and programmed to implement many
systolicalgorithms. The
systolicenvironment, by virtue of its emphasis on continuous, regular flow of data and fairly simple per-cell processing, imposes new design requirements for programmable processors which are quite different from those found in a general-purpose system. This paper describes the CMU PSC, a single-chip microprocessor suitable for use in groups of tens or hundreds for the efficient implementation of a broad variety of
systolic arrays. The processor has been fabricated in nMOS, and is undergoing testing.
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