A 1.2 V 4.5 mW 10 bit 8 MS/s cyclic-ADC for mobile video and sensor applications

A 10 bit 8 MS/s cyclic ADC without a dedicated sample and hold is presented. Op-amp sharing and a single ended reference buffer loaded with a resistive divider are used. For power saving the common-mode buffer was replaced by a simple low pass filter. The ADC consumes 4.5 mW and occupies 0.145 mm2. It is fabricated in a 130 nm 1.2 V CMOS process and achieves 57 dB SNDR for an 11 MHz input. The cyclic stage works with a 40 MHz clock which can be increased to 65 MHz where the effective number of bits is reduced to 8. A novel dynamic current switching technique is introduced to reduce the power consumption by 20%. The figure of merit (FOM) is about 0.37 pJ/conversion step.