VIPIC IC — Design and test aspects of the 3D pixel chip

We report on the design of the VIPIC IC ( Vertically Integrated PixelImaging Chip) designedfor X-ray Photon Correlation Spectroscopy(XPCS) experiments by FNAL in collaboration with AGH-UST. The VIPIC chip is a prototype matrix with 64 × 64 pixelswith 80 μm × 80 μm pixelsize and consists of two layers: analog and digital. The single analog pixelcell consists of a charge sensitive amplifier, a shaper, a single current discriminator and trim DACs. The simulated gain is 52 μV/e − , the noise ENC − rms (with C det = 100 fF) and the peaking time t p < 250 ns. The power consumption is 25 μW/ pixelin the analog part. The digital layer of the VIPIC integrated circuit is divided into 16 readout groups of pixelsread out in parallel via separate serial portswith nominal frequency of the 100 MHz clock using the LVDS standard. The readout within each group is zero-suppressed. The sparsification scheme (addresses of hit pixelsonly) allows a dead-timefree readout.