Device-deviation tolerant over-1 GHz clock distribution scheme with skew-immune race-free impulse latch circuits
1998
Clock skew(and jitter) is becoming the major obstacle to high-frequency
clockdistribution in sub-quarter micron CMOS LSIs, because
skewcannot be scaled down even by use of scaled devices and may significantly increase as a result of device and
operating environmentdeviations. To overcome this obstacle, the authors present
skew-immune race-free impulse latch circuits and a reduced-
skewring-type
clockingscheme. The 1 GHz
clocktest chip is integrated into a 6/spl times/6 mm/sup 2/ die with 0.18 /spl mu/m CMOS and double-layer-metal technology. The supply voltage is 1.8 V. The threshold voltage of the nMOS transistors is about 0.3 V and that of the pMOS transistors is about -0.3 V. 1 GHz global
clockdistribution shows less than 50 ps
clock skewfor those points on the chip.
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